Integrated circuits often require components having operating characteristics (e.g., resistance, capacitance, etc.) fabricated to a high degree of precision. For instance, the accuracy of a digital-to-analog (D/A) converter using binary weighted current sources depends on the matching accuracy of the transistors. Similarly, the accuracy of a charge redistribution analog-to-digital (A/D) convertor or D/A convertor depends on the matching accuracy of the capacitors. The component's characteristics, such as a capacitor's capacitance, used in the D/A or A/D converter must be fabricated to establish a precise relationship between the components to maintain correct weighting of the individual bits of the converter.
Variations in the operating characteristics of the components will adversely affect the ability of the converter to correctly convert a given input such as a digital word for a D/A converter or an analog voltage level for an A/D converter. In semiconductor circuit fabrication, processing variations often prevent components from having precisely fabricated operating characteristics. This problem is further compounded in a device such as in an A/D or D/A converter where the operating characteristics of a given component, in relation to the operating characteristics of other components, are critical. The greater the resolution of a given converter (e.g., the more bits that are involved in the conversion process), the greater the number of components that must be precisely matched. Experimentally, it has been proven that transistors, resistors and capacitors can be fabricated for a ratio matching accuracy (e.g., the relative characteristics of all the components required for a given application, such as all the resistors used in the conversion process for an A/D converter) of up to 10-bits (either input bits for a D/A converter or output bits for an A/D converter) with good yields. Yet, in sound processing applications for example, a conversion resolution of 20-bits or more is commonly required.
To fabricate reliably a D/A converter that can accurately convert a given input of greater than 10-bits, or fabricate reliably an A/D converter that can accurately convert a given input to an output of greater than 10-bits, requires a calibration process such as laser trimming to calibrate precisely the operating characteristics of components. Laser trimming is a calibration process where individual components of an integrated circuit are cut using a laser to alter specific physical characteristics (e.g., surface area) of the components. Reducing the surface area of a given component, also affects the operating characteristics of that component. By precisely measuring the operating characteristics of the component during the laser trimming process, the operating characteristics of the component can be precisely calibrated. However, laser trimming is expensive and time consuming in that it requires extra processing steps to complete the fabrication of the component. Additionally, laser trimming requires a special test setup and must be performed prior to packaging the integrated circuit. This introduces another problem in that some component values change after packaging due to factors such as stray capacitance of the packaging material or stress during the packaging process. For such cases, laser trimming cannot be used. The prior art teaches using an on-chip programmable memory to solve the above problems. The on-chip programmable memory may consist of fuse, EPROM or EEPROM circuits.
In practice, an integrated circuit is fabricated with additional components ("calibrating components") having an assortment of operating characteristics. During the calibration of the integrated circuit, either the fuses or the PROM circuits are used to selectively connect the calibrating components to the component that requires the calibration (the "calibrated component") until the operating characteristics of the combined components are precisely adjusted. For example, a capacitor (the calibrated component) may have several additional capacitors (the calibrating components) added in parallel until the precise required capacitance is obtained.
The problem with using EPROMs and EEPROMs to calibrate the operating characteristics of components is that the fabrication of EPROM and EEPROM memory circuits requires additional processing steps. A fuse can be fabricated during standard CMOS processing and is therefore less expensive to use for calibrating components than EPROM and EEPROM memory circuits.
One prior art method of calibrating a component uses a single fuse between the calibrated component and each individual calibrating component. Initially, the fuse operates as a short circuit between the calibrated component and the calibrating components. During the calibration of the component, the fuses are selectively opened (blown out) by passing a large current through the fuse. The components that are attached to the blown out fuse are physically disconnected from the calibrated component and thus do not affect the operating characteristics of the calibrated component.
A problem with using fuses to calibrate components is that each fuse requires a separate bond pad (input terminal) to enable the selective burning of each fuse. A large number of fuses may be required on one chip to enable a proper calibration of the critical components and it may not be possible to have a separate input terminal to selectively blow each fuse. To solve this problem, an on-chip decoder may be used to selectively address each fuse. However, the use of a decoder limits the current that can be used to blow a fuse. As a result of this limited current, a fuse may only be partially blown. In the single fuse method of calibrating a component (as discussed above), the partially blown fuse will have some unpredictable resistance which will alter the effect that an added component (e.g., the calibrating component) will have on the calibrated component. This results in an indeterminable output which destroys the utility of a calibrating circuit.
Another prior art method of calibrating components, which overcomes the problems of the single fuse method discussed above, uses a differential fuse circuit. Unlike the single fuse circuit, the differential fuse circuit has two fuses per calibrating component and the relative difference in the resistance value of the two fuses determines whether the calibrating component is used or not. In operation, only one of the two fuses is blown and only a relatively small difference in resistance between the blown and unblown fuse (remembering that even an unblown fuse has some measurable resistance) is required to set the output of the differential fuse circuit either to a "low" or a "high" potential. The potential at the output of the differential fuse circuit determines whether the calibrating component is used or not. Therefore, even if a fuse is only partially blown, the resistance of the partially blown fuse does not alter the effect of the calibrating component. The differential fuse circuit solves the problem that the single fuse circuit has with partially blown fuses but introduces another problem in that the differential fuse circuit of the prior art consumes from 5 to 10 .mu.A of current.
A differential fuse circuit is disclosed in U.S. Pat. No. 5,353,028 to Michiel de Wit ("the '028 patent"). The contents of the '028 patent are incorporated herein by reference.
FIG. 1 shows a differential fuse circuit as disclosed in the '028 patent. This differential fuse circuit comprises a bias circuit 20, a fuse circuit 10 and an invertor 13. The fuse circuit 10 comprises a first leg that is connect to a supply potential V.sub.SUPPLY through a first fuse 11, and a second leg that is connect to a supply potential V.sub.SUPPLY through a second fuse 12. The first and second leg are configured such that a current in a lower portion of the first leg will induce a current in a lower portion of the second leg. This is called a "current mirror" circuit since the current in the lower portion of the second leg "mirrors" the current in the lower portion of the first leg. Conversely, a current in the lower portion of the second leg does not induce a current in the lower portion of the first leg.
In operation, if the resistance of the second fuse 12 is made greater than the resistance of the first fuse 11 (e.g., the second fuse 12 is blown), there is essentially no current I.sub.2 in the upper portion of the second leg. The current I.sub.1 in the first leg is not affected by the second fuse 12 being blown and the current in the lower portion of the first leg induces a current in the lower portion of the second leg (due to the current mirror described above). Therefore, a node V.sub.f, which is connected between the upper and lower portion of the second leg, is essentially at the same potential as a reference supply V.sub.REF (e.g., a low potential) and the potential at an output node V.sub.o, which is connected to the node V.sub.f through the inverter 13, is at a high potential.
In this case, the current 12 through the second fuse 12 is small for a large resistance of the second fuse 12 (e.g., a blown fuse). The current I.sub.1 through the first fuse 11 is independent of the resistance of the blown second fuse 12 and depends on the bias current from the bias circuit 20. The current I.sub.1 is typically in the range of 5 to 10 .mu.A.
To set the potential at the output node V.sub.o low, the first fuse 11 is blown and thereby, there is essentially no current I.sub.1. Since essentially no current flows in the lower portion of the first leg of the fuse circuit 10, essentially no current flows in the lower portion of the second leg of the fuse circuit 10 (due to the current mirror effect). In this case, the current I.sub.2 (since the second fuse 12 is unblown) causes the node V.sub.f to be essentially at the same potential as V.sub.SUPPLY (e.g., high). Therefore, the potential at the output node V.sub.o is low.
When the first fuse 11 is blown and the second fuse 12 is intact (e.g., when the potential at the output node V.sub.o is low), current's I.sub.1 and I.sub.2 are small as long as the resistance of the first fuse 11 (the blown fuse) is large (e.g., greater than 2 M.OMEGA.). When the potential at the output node V.sub.o is high (e.g., when the first fuse 11 is unblown and the second fuse 12 is blown), the current I.sub.2 is low (due to the high resistance of the blown second fuse 12). The current I.sub. 1 (typically in the range of 5 to 10 .mu.A, as discussed above) is independent of the resistance of the blown second fuse 12 and depends on the bias circuit 20.
The differential fuse circuit of the prior art has several drawbacks. For example, using the prior art differential fuse circuit, an integrated circuit having N fuse circuits, with half the fuse circuits programmed "high" (e.g., the potential at the output node V.sub.o is high), consumes approximately (I.sub.1 .times.N/2) amps (not including the bias current or the current consumed by the rest of the integrated circuit). For the case when N is large, the fuse circuits will consume a large amount of current which may not be acceptable for many low current integrated circuit applications.
To solve the above problems, a new low current differential fuse circuit is hereby disclosed.
Therefore, it is an object of the present invention to provide a method of forming a low current differential fuse circuit which consumes less than 1 .mu.A of current (aside from bias current) when the potential at the output node V.sub.o is high or low (e.g., when either the first or second fuse is blown).
Another object of this invention is to provide an improved differential fuse circuit (e.g., a low current differential fuse circuit) which consumes less than 1 .mu.A.
A further object of this invention is to provide a circuit and a method of forming it that can be utilized to appropriately change the value of components without requiring additional processing steps.
A still further object of this invention is to provide a circuit configuration and a method of forming that circuit configuration, which can compensate for characteristic variations of integrated circuit components without requiring external means such as laser trimming.